-
Notifications
You must be signed in to change notification settings - Fork 6
/
a56.y
executable file
·2124 lines (1966 loc) · 47.5 KB
/
a56.y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
%{
/*******************************************************
*
* a56 - a DSP56001 assembler
*
* Written by Quinn C. Jensen
* July 1990
*
*******************************************************/
/*
* Copyright (C) 1990-1994 Quinn C. Jensen
*
* Permission to use, copy, modify, distribute, and sell this software
* and its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and
* that both that copyright notice and this permission notice appear
* in supporting documentation. The author makes no representations
* about the suitability of this software for any purpose. It is
* provided "as is" without express or implied warranty.
*
*/
/*
* a56.y - The YACC grammar for the assembler.
*
* Note: This module requires a "BIG" version of YACC. I had to
* recompile YACC in the largest mode available.
*
* Other notes:
*
* MOVEC, MOVEM and MOVEP must be used explicitly--MOVE can't yet figure
* out which form to use.
*
*/
#include "a56.h"
#include <math.h>
unsigned int w0, w1; /* workspace for the actual generated code */
BOOL uses_w1; /* says whether w1 is alive */
unsigned int pc; /* current program counter */
int seg; /* current segment P: X: Y: or L: */
int expr_seg; /* segment of current expression */
int just_rep = 0; /* keeps track of REP instruction */
int hot_rreg = -1; /* rreg loaded by prev inst. or -1 */
int hot_nreg = -1; /* nreg loaded by prev inst. or -1 */
int hot_mreg = -1; /* mreg loaded by prev inst. or -1 */
int prev_hot_rreg = -1; /* rreg loaded by prev inst. or -1 */
int prev_hot_nreg = -1; /* nreg loaded by prev inst. or -1 */
int prev_hot_mreg = -1; /* mreg loaded by prev inst. or -1 */
int substatement = 0; /* in a substatement */
BOOL long_symbolic_expr = FALSE; /* a parser flag */
char *new_include = NULL; /* file to be included */
/* listing stuff */
char segs[] = "uPXYL*";
extern BOOL list_on_next; /* listing to turn on or off */
BOOL list_on; /* listing on at the moment */
extern char *cur_line; /* points to line being lex'd */
char list_buf[1024 + 80]; /* listing buffer */
char list_buf2[1024 + 80]; /* listing buffer for two-line code */
BOOL uses_buf2 = FALSE; /* list_buf2 is alive */
BOOL list_print_line = FALSE; /* whether or not to print line in listing */
char *spaces(), *luntab();
struct n binary_op();
struct n unary_op();
struct n sym_ref();
#define R_R6 0x0001
#define R_R5 0x0002
#define R_R4 0x0004
#define R_DATA_ALU_ACCUM 0x0008
#define R_CTL_REG 0x0010
#define R_FUNKY_CTL_REG 0x0020
#define R_SDX 0x0040
#define R_SDY 0x0080
#define R_LSD 0x0100
#define R_AB 0x0200
#define R_XREG 0x0400
#define R_YREG 0x0800
/* registers to which short immediate move is an unsigned int */
#define R_UINT 0x1000
/* registers to which short immediate move is an signed frac */
#define R_SFRAC 0x2000
%}
%union {
int ival; /* integer value */
struct n n; /* just like in struct sym */
double dval; /* floating point value */
char *sval; /* string */
int cval; /* character */
char cond; /* condition */
struct regs {
int r6, r5, r4, data_alu_accum, ctl_reg, funky_ctl_reg;
int sdx, sdy, lsd, ab, xreg, yreg;
int flags;
} regs;
struct ea {
int mode;
int ext;
int pp;
} ea;
}
%token <n> CHEX CDEC FRAC
%token <ival> AREG BREG MREG NREG RREG XREG YREG
%token <ival> OP OPA OPP
%token <cond> OP_JCC OP_JSCC OP_TCC
%token <sval> SYM
%token <sval> STRING
%token <cval> CHAR
%token XMEM
%token YMEM
%token LMEM
%token PMEM
%token AAAA
%token A10
%token BBBB
%token B10
%token AABB
%token BBAA
%token XXXX
%token YYYY
%token SR
%token MR
%token CCR
%token OMR
%token SP
%token SSH
%token SSL
%token LA
%token LC
%token EOL
%token EOS
%token LEXBAD
%token OP_ABS
%token OP_ADC
%token OP_ADD
%token OP_ADDL
%token OP_ADDR
%token OP_ASL
%token OP_ASR
%token OP_CLR
%token OP_CMP
%token OP_CMPM
%token OP_DEC
%token OP_DIV
%token OP_INC
%token OP_MAC
%token OP_MACR
%token OP_MPY
%token OP_MPYR
%token OP_NEG
%token OP_NORM
%token OP_RND
%token OP_SBC
%token OP_SUB
%token OP_SUBL
%token OP_SUBR
%token OP_TFR
%token OP_TST
%token OP_AND
%token OP_ANDI
%token OP_EOR
%token OP_LSL
%token OP_LSR
%token OP_NOT
%token OP_OR
%token OP_ORI
%token OP_ROL
%token OP_ROR
%token OP_BCLR
%token OP_BSET
%token OP_BCHG
%token OP_BTST
%token OP_DO
%token OP_ENDDO
%token OP_LUA
%token OP_MOVE
%token OP_MOVEC
%token OP_MOVEM
%token OP_MOVEP
%token OP_ILLEGAL
%token OP_INCLUDE
%token OP_JMP
%token OP_JCLR
%token OP_JSET
%token OP_JSR
%token OP_JSCLR
%token OP_JSSET
%token OP_NOP
%token OP_REP
%token OP_RESET
%token OP_RTI
%token OP_RTS
%token OP_STOP
%token OP_SWI
%token OP_WAIT
%token OP_EQU
%token OP_ORG
%token OP_DC
%token OP_DS
%token OP_DSM
%token OP_END
%token OP_PAGE
%token OP_PSECT
%token OP_ALIGN
%token OP_INT
%token SHL
%token SHR
%token OP_PI
%token OP_SIN
%token OP_COS
%token OP_TAN
%token OP_ATAN
%token OP_ASIN
%token OP_ACOS
%token OP_EXP
%token OP_LN
%token OP_LOG
%token OP_POW
%type <n> num num_or_sym
%type <n> num_or_sym_expr
%type <n> expr
%type <n> ix
%type <n> ix_long
%type <ival> abs_addr abs_short_addr io_short_addr
%type <ival> a_b x_or_y ea b5_10111_max
%type <ival> p6_ean_a6 ea_no_ext p6_ea_a6 ea_a6 ea_a12
%type <ival> ea_short
%type <ival> prog_ctl_reg
%type <ival> op8_1 op8_2 op8_3 op8_4 op8_5 op8_6 op8_7 op8_8
%type <ival> mpy_arg mpy_srcs plus_minus
%type <ival> sd3
%type <ival> funky_ctl_reg tcc_sd space
%type <sval> opt_label
%type <regs> regs
%type <ea> movep_ea_pp
%left '|'
%left '^'
%left SHL SHR
%left '&'
%left '+' '-'
%left '*' '/' '%'
%right '~'
%start input
%%
/*%%%********************* top syntax ***********************/
input : /* empty */
| input statement
;
statement
: good_stuff EOL
{
if(pass == 2 && list_on && list_print_line) {
printf(ldebug ? "\n(%s|%s)\n" : "%s%s\n",
list_buf, substatement == 0 ? luntab(cur_line) : "");
if(uses_buf2)
printf(ldebug ? "\n(%s|)\n" : "%s\n",
list_buf2);
list_buf[0] = list_buf2[0] = '\0';
}
curline++;
uses_buf2 = FALSE;
list_print_line = TRUE;
list_on = list_on_next;
substatement = 0;
if(NOT check_psect(seg, pc) && pass == 2)
yyerror("%04X: psect violation", pc);
}
| good_stuff EOS
{
if(pass == 2 && list_on && list_print_line) {
printf(ldebug ? "\n(%s" : "%s", list_buf);
if(substatement == 0)
printf(ldebug ? "|%s)\n" : "%s\n", luntab(cur_line));
else
printf(ldebug ? ")\n" : "\n");
if(uses_buf2)
printf(ldebug ? "\n(%s|)\n" : "%s\n",
list_buf2);
list_buf[0] = list_buf2[0] = '\0';
}
substatement++;
uses_buf2 = FALSE;
list_print_line = TRUE;
list_on = list_on_next;
if(NOT check_psect(seg, pc) && pass == 2)
yyerror("%04X: psect violation", pc);
}
| error EOL
{curline++; substatement = 0;}
;
good_stuff
: /* empty */
{sprintf(list_buf, "%s", spaces(0));}
| cpp_droppings
{list_print_line = FALSE;}
| assembler_ops
{long_symbolic_expr = FALSE;}
| label_field operation_field
{char *printcode();
if(pass == 2) {
gencode(seg, pc, w0);
sprintf(list_buf, "%c:%04X %s ", segs[seg], pc, printcode(w0));
pc++;
if(uses_w1) {
gencode(seg, pc, w1);
sprintf(list_buf2, "%c:%04X %s", segs[seg], pc,
printcode(w1 & 0xFFFFFF));
uses_buf2++;
pc++;
}
} else {
pc++;
if(uses_w1)
pc++;
}
w0 = w1 = 0; uses_w1 = FALSE;
long_symbolic_expr = FALSE;}
| SYM
{sym_def($1, INT, seg, pc);
free($1);
if(pass == 2 && list_on) {
sprintf(list_buf, "%c:%04X%s", segs[seg], pc, spaces(14-8));
long_symbolic_expr = FALSE;
}}
;
cpp_droppings
: '#' num STRING
{if(strlen($3) > 0)
curfile = $3;
else
curfile = "<stdin>";
curline = $2.val.i - 1;}
;
assembler_ops
: SYM OP_EQU expr
{sym_def($1, $3.type, ANY, $3.val.i, $3.val.f);
free($1);
if(pass == 2 && list_on) {
if($3.type == INT)
sprintf(list_buf, "%06X%s",
$3.val.i & 0xFFFFFF,
spaces(14-8));
else
sprintf(list_buf, "%10g%s", $3.val.f,
spaces(14-4));
}}
| OP_ALIGN expr
{int ival = n2int($2);
if($2.type == UNDEF) {
yyerror("illegal forward reference");
} else if (ival <= 1) {
yyerror("%d: illegal alignment", ival);
} else {
if(pc % ival != 0)
pc += ival - pc % ival;
}
if(pass == 2 && list_on)
sprintf(list_buf, "%c:%04X%s", segs[seg], pc,
spaces(14-8));
}
| OP_PSECT SYM
{struct psect *pp = find_psect($2);
if(NOT pp) {
if(pass == 2)
yyerror("%s: undefined psect", $2);
} else {
seg = pp->seg;
pc = pp->pc;
set_psect(pp);
if(pass == 2 && list_on)
sprintf(list_buf, "%c:%04X%s", segs[seg], pc,
spaces(14-8));
}
free($2);}
| OP_PSECT SYM space expr ':' expr
{new_psect($2, $3, n2int($4), n2int($6));
if(pass == 2 && list_on)
sprintf(list_buf, "%c:%04X %04X%s",
segs[$3], n2int($4), n2int($6), spaces(14-8+4+1));
}
| OP_ORG space expr
{pc = n2int($3);
seg = $2;
if(pass == 2 && list_on)
sprintf(list_buf, "%c:%04X%s", segs[seg], pc,
spaces(14-8));
}
| OP_ORG space expr ',' space expr
{pc = n2int($3);
seg = $2;
if(pass == 2 && list_on)
sprintf(list_buf, "%c:%04X%s", segs[seg], pc,
spaces(14-8));
}
| label_field OP_DC dc_list
| label_field OP_DS expr
{pc += n2int($3);
if(pass == 2 && list_on)
sprintf(list_buf, "%c:%04X%s", segs[seg], pc,
spaces(14-8));
}
| opt_label OP_DSM expr
{int size = n2int($3);
if(size)
{ int align = 1;
while(align < size)
align <<= 1;
pc += (align - (pc % align));
}
if($1)
{ sym_def($1, INT, seg, pc);
free($1);
}
pc += size;
}
| OP_PAGE num ',' num ',' num ',' num
{if(pass == 2 && list_on) {
sprintf(list_buf, "%s", spaces(0));
}}
| OP_INCLUDE STRING
{if(pass == 2 && list_on) {
printf(ldebug ? "\n(%s|%s)\n" : "%s%s\n",
spaces(0), luntab(cur_line));
list_print_line = FALSE;
}
include($2); /* free($2); */
}
| OP_END
{if(pass == 2 && list_on) {
sprintf(list_buf, "%s", spaces(0));
}}
;
dc_list
: dc_list ',' dc_stuff
| dc_stuff
;
dc_stuff
: STRING
{int len = strlen($1), i; char *cp; w0 = 0;
if(len % 3 == 2)
len++; /* force empty word */
for(i = 0, cp = $1; i < len; i++, cp++) {
w0 |= (*cp & 0xFF) << (2 - (i % 3)) * 8;
if(i % 3 == 2 || i == len - 1) {
if(pass == 2) {
if(list_on) sprintf(list_buf, "%c:%04X %06X%s",
segs[seg], pc, w0,
spaces(14-6+5));
gencode(seg, pc, w0);
}
pc++; w0 = 0;
}
}
free($1);}
| expr
{int frac = n2frac($1);
if(pass == 2) {
if(list_on) {
sprintf(list_buf, "%c:%04X %06X%s", segs[seg], pc,
frac & 0xFFFFFF, spaces(14-6+5));
}
gencode(seg, pc, frac);
}
pc++;}
space
: PMEM
{$$ = PROG;}
| XMEM
{$$ = XDATA;}
| YMEM
{$$ = YDATA;}
| LMEM
{$$ = LDATA;}
;
label_field
: SYM
{sym_def($1, INT, seg, pc);
free($1);}
| /* empty */
;
opt_label
: SYM {$$ = $1;}
| /* empty */ {$$ = NULL;}
;
operation_field
: operation
{prev_hot_rreg = hot_rreg;
prev_hot_nreg = hot_nreg;
prev_hot_mreg = hot_mreg;
hot_rreg = hot_nreg = hot_mreg = -1;
if(just_rep)
just_rep--;}
;
operation
: no_parallel
| parallel_ok
{w0 |= 0x200000;}
| parallel_ok parallel_move
;
/*%%%************* instructions that allow parallel moves ****************/
parallel_ok
:
OP_MPY mpy_arg
{w0 |= 0x80 | $2 << 2;}
| OP_MPYR mpy_arg
{w0 |= 0x81 | $2 << 2;}
| OP_MAC mpy_arg
{w0 |= 0x82 | $2 << 2;}
| OP_MACR mpy_arg
{w0 |= 0x83 | $2 << 2;}
| OP_SUB op8_1
{w0 |= 0x04 | $2 << 3;}
| OP_ADD op8_1
{w0 |= 0x00 | $2 << 3;}
| OP_MOVE
{w0 |= 0x00;}
| OP_TFR op8_2
{w0 |= 0x01 | $2 << 3;}
| OP_CMP op8_2
{w0 |= 0x05 | $2 << 3;}
| OP_CMPM op8_2
{w0 |= 0x07 | $2 << 3;}
| OP_RND op8_3
{w0 |= 0x11 | $2 << 3;}
| OP_ADDL op8_3
{w0 |= 0x12 | $2 << 3;}
| OP_CLR op8_3
{w0 |= 0x13 | $2 << 3;}
| OP_SUBL op8_3
{w0 |= 0x16 | $2 << 3;}
| OP_NOT op8_3
{w0 |= 0x17 | $2 << 3;}
| OP_ADDR op8_4
{w0 |= 0x02 | $2 << 3;}
| OP_TST op8_4
{w0 |= 0x03 | $2 << 3;}
| OP_SUBR op8_4
{w0 |= 0x06 | $2 << 3;}
| OP_AND op8_5
{w0 |= 0x46 | $2 << 3;}
| OP_OR op8_5
{w0 |= 0x42 | $2 << 3;}
| OP_EOR op8_5
{w0 |= 0x43 | $2 << 3;}
| OP_ASR op8_6
{w0 |= 0x22 | $2 << 3;}
| OP_LSR op8_6
{w0 |= 0x23 | $2 << 3;}
| OP_ABS op8_6
{w0 |= 0x26 | $2 << 3;}
| OP_ROR op8_6
{w0 |= 0x27 | $2 << 3;}
| OP_ASL op8_7
{w0 |= 0x32 | $2 << 3;}
| OP_LSL op8_7
{w0 |= 0x33 | $2 << 3;}
| OP_NEG op8_7
{w0 |= 0x36 | $2 << 3;}
| OP_ROL op8_7
{w0 |= 0x37 | $2 << 3;}
| OP_ADC op8_8
{w0 |= 0x21 | $2 << 3;}
| OP_SBC op8_8
{w0 |= 0x25 | $2 << 3;}
;
mpy_arg : plus_minus mpy_srcs ',' a_b
{$$ = $1 | $4 << 1 | $2 << 2;}
;
plus_minus
: '+'
{$$ = 0;}
| '-'
{$$ = 1;}
|
{$$ = 0;}
;
mpy_srcs
: XREG ',' XREG
{switch ($1 << 4 | $3) {
case 0x00: $$ = 0x0; break;
case 0x01:
case 0x10: $$ = 0x2; break;
case 0x11:
yyerror("illegal source operands");
break;
}}
| YREG ',' YREG
{switch ($1 << 4 | $3) {
case 0x00: $$ = 0x1; break;
case 0x01:
case 0x10: $$ = 0x3; break;
case 0x11:
yyerror("illegal source operands");
break;
}}
| XREG ',' YREG
{switch ($1 << 4 | $3) {
case 0x00: $$ = 0x5; break;
case 0x01: $$ = 0x4; break;
case 0x10: $$ = 0x6; break;
case 0x11: $$ = 0x7; break;
}}
| YREG ',' XREG
{switch ($1 << 4 | $3) {
case 0x00: $$ = 0x5; break;
case 0x01: $$ = 0x6; break;
case 0x10: $$ = 0x4; break;
case 0x11: $$ = 0x7; break;
}}
;
op8_1 : BBBB ',' AAAA
{$$ = 0x2;}
| AAAA ',' BBBB
{$$ = 0x3;}
| XXXX ',' a_b
{$$ = 0x4 | $3;}
| YYYY ',' a_b
{$$ = 0x6 | $3;}
| XREG ',' a_b
{$$ = 0x8 | $1 << 2 | $3;}
| YREG ',' a_b
{$$ = 0xA | $1 << 2 | $3;}
;
op8_2 : BBBB ',' AAAA
{$$ = 0x0;}
| AAAA ',' BBBB
{$$ = 0x1;}
| XREG ',' a_b
{$$ = 0x8 | $1 << 2 | $3;}
| YREG ',' a_b
{$$ = 0xA | $1 << 2 | $3;}
;
op8_3 : AAAA
{$$ = 0x0;}
| BBBB
{$$ = 0x1;}
| BBBB ',' AAAA
{$$ = 0x0;}
| AAAA ',' BBBB
{$$ = 0x1;}
;
op8_4 : op8_3
{$$ = $1;}
;
op8_5 : XREG ',' a_b
{$$ = 0x0 | $1 << 2 | $3;}
| YREG ',' a_b
{$$ = 0x2 | $1 << 2 | $3;}
;
op8_6 : a_b
{$$ = $1;}
;
op8_7 : a_b
{$$ = $1;}
;
op8_8 : XXXX ',' a_b
{$$ = 0x0 | $3;}
| YYYY ',' a_b
{$$ = 0x2 | $3;}
;
a_b : AAAA
{$$ = 0;}
| BBBB
{$$ = 1;}
;
no_parallel
: control_inst
{if(just_rep == 1)
yyerror("instruction not allowed after REP");}
| bit_inst
| move_inst
| arith_inst
;
/*%%%************** non-parallel arithmetic and logical ********************/
arith_inst
: OP_NORM RREG ',' a_b
{w0 |= 0x01D815 | $2 << 8 | $4 << 3;}
| OP_DIV sd3
{w0 |= 0x018040 | $2 << 3;}
| or_op ix ',' funky_ctl_reg
{w0 |= 0x0000F8 | (n2int($2) & 0xFF) << 8 | $4;}
| and_op ix ',' funky_ctl_reg
{w0 |= 0x0000B8 | (n2int($2) & 0xFF) << 8 | $4;}
| OP_DEC a_b
{w0 |= 0x00000A | $2;}
| OP_INC a_b
{w0 |= 0x000008 | $2;}
;
or_op : OP_OR
| OP_ORI
;
and_op : OP_AND
| OP_ANDI
;
/*%%%******************************* control instructions **********************/
control_inst
: OP_JSCC ea_a12
{if($2) {
w0 |= 0x0BC0A0 | $1 << 0;
} else {
w0 |= 0x0F0000 | $1 << 12;
}}
| OP_JCC ea_a12
{if($2) {
w0 |= 0x0AC0A0 | $1 << 0;
} else {
w0 |= 0x0E0000 | $1 << 12;
}}
| OP_JSR ea_a12
{if($2) {
w0 |= 0x0BC080;
} else {
w0 |= 0x0D0000;
}}
| OP_JMP ea_a12
{if($2) {
w0 |= 0x0AC080;
} else {
w0 |= 0x0C0000;
}}
| OP_JSSET control_args
{w0 |= 0x0B0020;}
| OP_JSCLR control_args
{w0 |= 0x0B0000;}
| OP_JSET control_args
{w0 |= 0x0A0020;}
| OP_JCLR control_args
{w0 |= 0x0A0000;}
| OP_REP rep_args
{just_rep = 2;}
| OP_DO do_args
{uses_w1++;}
| OP_ENDDO
{w0 |= 0x00008C;}
| OP_STOP
{w0 |= 0x000087;}
| OP_WAIT
{w0 |= 0x000086;}
| OP_RESET
{w0 |= 0x000084;}
| OP_RTS
{w0 |= 0x00000C;}
| OP_SWI
{w0 |= 0x000006;}
| OP_ILLEGAL
{w0 |= 0x000005;}
| OP_RTI
{w0 |= 0x000004;}
| OP_NOP
{w0 |= 0x000000;
just_rep = 0;}
;
do_args
: ix ',' abs_addr
{int ival = n2int($1);
w0 |= 0x060080 | (ival & 0xFF) << 8 | (ival & 0xF00)>> 8;
if(ival > 0xFFF && pass == 2) {
yywarning("warning: immediate operand truncated");
}
w1 |= $3-1;}
| regs ',' abs_addr
{w0 |= 0x06C000 | $1.r6 << 8;
hot_rreg = hot_nreg = hot_mreg = -1;
w1 |= $3-1;}
| x_or_y ea_no_ext ',' abs_addr
{w0 |= 0x064000 | $2 << 8 | $1 << 6;
w1 |= $4-1;}
| x_or_y abs_short_addr ',' abs_addr /* allow forced */
{w0 |= 0x060000 | ($2 & 0x3F) << 8 | $1 << 6;
/*
* $$$ oops, can't check expr_seg because both abs_short_addr and
* abs_addr touch it
*/
if($2 > 0x003F && pass == 2)
yywarning("warning: address operand truncated");
w1 |= $4-1;}
| x_or_y abs_addr ',' abs_addr
{w0 |= 0x060000 | ($2 & 0x3F) << 8 | $1 << 6;
/*
* $$$ oops, can't check expr_seg because both abs_short_addr and
* abs_addr touch it
*/
if($2 > 0x003F && pass == 2)
yywarning("warning: address operand truncated");
w1 |= $4-1;}
;
rep_args
: ix
{int ival = n2int($1);
w0 |= 0x0600A0 | (ival & 0xFF) << 8 | (ival & 0xF00)>> 8;
if(ival > 0xFFF && pass == 2) {
yywarning("warning: immediate operand truncated");
}}
| regs
{w0 |= 0x06C020 | $1.r6 << 8;
hot_rreg = hot_nreg = hot_mreg = -1;}
| x_or_y ea_no_ext
{w0 |= 0x064020 | $1 << 6 | $2 << 8;}
| x_or_y abs_addr
{w0 |= 0x060020 | $1 << 6 | ($2 & 0x3F) << 8;
if(expr_seg != ANY && ($1 == 0 && expr_seg != XDATA ||
$1 == 1 && expr_seg != YDATA))
yywarning("warning: space mismatch");
if($2 > 0x003F && pass == 2)
yywarning("warning: address operand truncated");
}
| x_or_y abs_short_addr /* forced */
{w0 |= 0x060020 | $1 << 6 | ($2 & 0x3F) << 8;
if(expr_seg != ANY && ($1 == 0 && expr_seg != XDATA ||
$1 == 1 && expr_seg != YDATA))
yywarning("warning: space mismatch");
if($2 > 0x003F && pass == 2)
yywarning("warning: address operand truncated");
}
;
control_args
: b5_10111_max ',' x_or_y p6_ean_a6 ',' abs_addr
{w0 |= $1 << 0 | $3 << 6;
uses_w1++;
w1 = $6;}
| b5_10111_max ',' regs ',' abs_addr
{w0 |= 0x00C000 | $1 << 0 | $3.r6 << 8;
hot_rreg = hot_nreg = hot_mreg = -1;
uses_w1++;
w1 = $5;}
;
p6_ean_a6
: abs_addr /* in pass 2 can always discern size. */
/* Sometimes in pass one, too. But since */
/* address extension is always used for the */
/* branch target, pass 1 can assume the */
/* symbol value will fit; warning in pass 2 */
/* if it doesn't */
{if($1 != -1) { /* symbol defined */
w0 |= ($1 & 0x3F) << 8;
if($1 >= 0xFFC0) {
w0 |= 0x008080;
} else {
w0 |= 0x000080;
if($1 > 0x003F && pass == 2)
yywarning("warning: address operand truncated");
}
}}
| abs_short_addr
{if($1 != -1) {
if($1 > 0x3F && pass == 2)
yywarning("warning: address operand truncated");
w0 |= 0x000080 | ($1 & 0x3F) << 8;
}}
| io_short_addr
{if($1 != -1) {
if($1 < 0xFFC0 && pass == 2)
yywarning("warning: address operand truncated");
w0 |= 0x008080 | ($1 & 0x3F) << 8;
}}
| ea_no_ext
{w0 |= 0x004080 | $1 << 8;}
;
/*%%%**************************** bit instructions ***************************/
bit_inst
: OP_BTST bit_args
{w0 |= 0x0B0020;}
| OP_BCHG bit_args
{w0 |= 0x0B0000;}
| OP_BSET bit_args
{w0 |= 0x0A0020;}
| OP_BCLR bit_args
{w0 |= 0x0A0000;}
;
bit_args
: b5_10111_max ',' x_or_y p6_ea_a6
{w0 |= $1 << 0 | $3 << 6;
}
| b5_10111_max ',' regs
{w0 |= 0x00C040 | $1 << 0 | $3.r6 << 8;}
;
p6_ea_a6
: io_short_addr /* must be forced to tell from abs_addr */
{if($1 != -1) {
w0 |= ($1 & 0x3F) << 8 | 0x008000;
if($1 < 0xFFC0 && pass == 2)
yywarning("warning: address operand truncated");
}}
| abs_short_addr /* must be forced to tell from abs_addr */
{if($1 != -1) {
w0 |= ($1 & 0x3F) << 8 | 0x000000;
if($1 > 0x003F && pass == 2)
yywarning("warning: address operand truncated");
}}
| ea /* can use abs_addr */
{w0 |= 0x004000;}
;
/*%%%************************** move instructions **********************/
move_inst
: OP_MOVEP movep_args
| OP_MOVEM movem_args
| OP_MOVEC movec_args
| OP_LUA ea_short ',' regs
{w0 |= 0x044010 | $2 << 8 | $4.r4;}
| OP_TCC tcc_args
{w0 |= $1 << 12;}
;
tcc_args
: tcc_sd
{w0 |= 0x020000 | $1 << 3;}
| tcc_sd RREG ',' RREG
{w0 |= 0x030000 | $1 << 3 | $2 << 8 | $4;}
;
tcc_sd
: regs /* a_b */ ',' regs /* a_b */
{hot_rreg = hot_nreg = hot_mreg = -1;
if($1.flags & R_AB && $3.flags & R_AB) {
if($1.ab == $3.ab)
yyerror("source and dest must be different");
$$ = $3.ab;
} else if($1.flags & R_XREG && $3.flags & R_AB) {
$$ = 0x8 | $1.xreg << 2 | $3.ab;
} else if($1.flags & R_YREG && $3.flags & R_AB) {
$$ = 0xA | $1.yreg << 2 | $3.ab;
} else
yyerror("illegal TCC operands");
}
;
sd3 : regs /* XREG */ ',' regs /* a_b */
{hot_rreg = hot_nreg = hot_mreg = -1;
if($1.flags & R_XREG && $3.flags & R_AB) {
$$ = $1.xreg << 2 | $3.ab;