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I managed to compile and simulate caravel with verilator while removing the chip io. Since verilator still can't compile any buffer with drive strength, we could replace chip_io with behavior model for verilator simulating. Verilator would speed up simulation time for the user projects.
The text was updated successfully, but these errors were encountered:
I managed to compile and simulate caravel with verilator while removing the chip io. Since verilator still can't compile any buffer with drive strength, we could replace chip_io with behavior model for verilator simulating. Verilator would speed up simulation time for the user projects.
The text was updated successfully, but these errors were encountered: