From cd981e27943b802773df5590e8c0a9f21dc48915 Mon Sep 17 00:00:00 2001 From: Yoann Pruvost Date: Tue, 19 Sep 2023 11:37:30 +0800 Subject: [PATCH] RVFI - Adding valid bit to mem req id to catch only the intended register write --- bhv/cv32e40p_rvfi.sv | 27 ++++++++++++++++++++------- bhv/insn_trace.sv | 4 ++++ 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/bhv/cv32e40p_rvfi.sv b/bhv/cv32e40p_rvfi.sv index e19866958..97545a60f 100644 --- a/bhv/cv32e40p_rvfi.sv +++ b/bhv/cv32e40p_rvfi.sv @@ -1351,12 +1351,14 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; end if (trace_wb.m_valid && !s_skip_wb) begin if (r_pipe_freeze_trace.rf_we_wb) begin - if((trace_wb.m_rd_addr[0] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[0])) begin - trace_wb.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb; + if((trace_wb.m_rd_addr[0] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[0]) && trace_wb.m_mem_req_id_valid[0]) begin + trace_wb.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb; trace_wb.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb; - end else if (trace_wb.m_2_rd_insn && (trace_wb.m_rd_addr[1] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[1])) begin - trace_wb.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb; + trace_wb.m_mem_req_id_valid[0] = 1'b0; + end else if (trace_wb.m_2_rd_insn && (trace_wb.m_rd_addr[1] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[1]) && trace_wb.m_mem_req_id_valid[1]) begin + trace_wb.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb; trace_wb.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb; + trace_wb.m_mem_req_id_valid[1] = 1'b0; end end @@ -1395,14 +1397,16 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; if (r_pipe_freeze_trace.regfile_we_lsu) begin ->e_dev_commit_rf_to_ex_4; - if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_ex.m_got_ex_reg)) begin + if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_ex.m_got_ex_reg) && trace_ex.m_mem_req_id_valid[0]) begin trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb; trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb; trace_ex.m_got_first_data = 1'b1; - end else if (cnt_data_resp == trace_ex.m_mem_req_id[1]) begin + trace_ex.m_mem_req_id_valid[0] = 1'b0; + end else if ((cnt_data_resp == trace_ex.m_mem_req_id[1]) && trace_ex.m_mem_req_id_valid[1]) begin trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb; trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb; trace_ex.m_got_first_data = 1'b1; + trace_ex.m_mem_req_id_valid[1] = 1'b0; end end @@ -1543,6 +1547,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; cnt_data_req = cnt_data_req + 1; trace_id.m_is_memory = 1'b1; trace_id.m_mem_req_id[0] = cnt_data_req; + trace_id.m_mem_req_id_valid[0] = 1'b1; trace_id.m_mem.addr = r_pipe_freeze_trace.data_addr_pmp; if (r_pipe_freeze_trace.data_misaligned) begin @@ -1555,6 +1560,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; trace_id.m_data_missaligned = 1'b1; trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0]; trace_id.m_mem_req_id[0] = cnt_data_req; + trace_id.m_mem_req_id_valid[1] = 1'b1; end end else begin trace_id.m_mem.rmask = be_to_mask(r_pipe_freeze_trace.lsu_data_be); //'1; @@ -1562,6 +1568,8 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; if (trace_id.m_got_ex_reg) begin // Shift index 0 to 1 trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0]; trace_id.m_mem_req_id[0] = 0; + trace_id.m_mem_req_id_valid[1] = 1'b1; + trace_id.m_mem_req_id_valid[0] = 1'b0; end end hwloop_to_id(); @@ -1580,6 +1588,8 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; if (trace_id.m_mem_req_id[0] != 0) begin trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0]; trace_id.m_mem_req_id[0] = 0; + trace_id.m_mem_req_id_valid[0] = 1'b0; + trace_id.m_mem_req_id_valid[1] = 1'b1; end end end //trace_if.m_valid @@ -1609,7 +1619,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; cnt_data_req = cnt_data_req + 1; trace_id.m_is_memory = 1'b1; trace_id.m_mem_req_id[0] = cnt_data_req; - + trace_id.m_mem_req_id_valid[0] = 1'b1; trace_id.m_mem.addr = r_pipe_freeze_trace.data_addr_pmp; if (r_pipe_freeze_trace.data_misaligned) begin cnt_data_req = cnt_data_req + 1; @@ -1620,11 +1630,14 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb; trace_id.m_data_missaligned = 1'b1; trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0]; trace_id.m_mem_req_id[0] = cnt_data_req; + trace_id.m_mem_req_id_valid[1] = 1'b1; end end if (trace_id.m_got_ex_reg) begin // Shift index 0 to 1 trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0]; trace_id.m_mem_req_id[0] = 0; + trace_id.m_mem_req_id_valid[0] = 1'b0; + trace_id.m_mem_req_id_valid[1] = 1'b1; end end else if (r_pipe_freeze_trace.rf_we_wb && !r_pipe_freeze_trace.ex_reg_we) begin trace_id.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb; diff --git a/bhv/insn_trace.sv b/bhv/insn_trace.sv index f73e98145..afdb27c00 100644 --- a/bhv/insn_trace.sv +++ b/bhv/insn_trace.sv @@ -34,6 +34,7 @@ logic m_is_apu_ok; integer m_apu_req_id; integer m_mem_req_id[1:0]; + logic [ 1:0] m_mem_req_id_valid; logic m_data_missaligned; logic m_got_first_data; logic m_got_ex_reg; @@ -150,6 +151,7 @@ this.m_apu_req_id = 0; this.m_mem_req_id[0] = 0; this.m_mem_req_id[1] = 0; + this.m_mem_req_id_valid = '0; this.m_trap = 1'b0; this.m_fflags_we_non_apu = 1'b0; this.m_frm_we_non_apu = 1'b0; @@ -208,6 +210,7 @@ this.m_apu_req_id = 0; this.m_mem_req_id[0] = 0; this.m_mem_req_id[1] = 0; + this.m_mem_req_id_valid = '0; this.m_data_missaligned = 1'b0; this.m_got_first_data = 1'b0; this.m_got_ex_reg = 1'b0; @@ -272,6 +275,7 @@ this.m_is_apu_ok = m_source.m_is_apu_ok; this.m_apu_req_id = m_source.m_apu_req_id; this.m_mem_req_id = m_source.m_mem_req_id; + this.m_mem_req_id_valid = m_source.m_mem_req_id_valid; this.m_data_missaligned = m_source.m_data_missaligned; this.m_got_first_data = m_source.m_got_first_data; this.m_got_ex_reg = m_source.m_got_ex_reg;