This document describes the proposed vector dot product extensions for RISC-V.
Convolution operations have seen considerable speedup on other microprocessor architectures with the adoption of specialized dot-product instructions. Such convolutions are used in many AI/ML, image-processing, and DSP algorithms. These algorithms can be found in benchmark suites which are used to measure the relative performance of microprocessor cores with different ISAs against each other. This suite of vector dot product extensions is designed to bring RISC-V vector performance up to or to exceed the level of the competition, depending on the implementation vector-length and number of vector ALUs.
The dot product operation is defined for four INT8 values held in a 32-bit element group with an accumulation back into a single 32-bit value with quad-widening. The dot-product operation takes the 8-bit values at the same index from each source and multiplies them together. The four products are summed together and accumulated into the 32-bit element of the destination register. If the instruction variant has any signed source data then the accumulation is performed into a signed value.
Given that the source data is 8-bits and accumulation is performed into 32-bits, it is presumed that overflow is infrequent and thus no saturation option has been provided.
To save on opcode encoding space the unsigned-signed vector-vector variant is not encoded; it is always possible to swap the order of the input operands to the signed-unsigned vector-vector variant.