mark some things private.

kivikakk · May 31, 2024 · faeb43b · faeb43b
1 parent fcb6259
commit faeb43b
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Showing 10 changed files with 14 additions and 13 deletions.
diff --git a/src/main/scala/ee/hrzn/chryse/ChryseScallopConf.scala b/src/main/scala/ee/hrzn/chryse/ChryseScallopConf.scala
@@ -4,7 +4,7 @@ import org.rogach.scallop.ScallopConf
 import org.rogach.scallop.Subcommand
 
 // TODO (Scallop): Show parent version string on subcommand help.
-class ChryseScallopConf(chryse: ChryseApp, args: Array[String])
+private[chryse] class ChryseScallopConf(chryse: ChryseApp, args: Array[String])
     extends ScallopConf(args) {
   private val appVersion = getClass().getPackage().getImplementationVersion()
   val versionBanner = s"${chryse.name} $appVersion (Chryse " +

diff --git a/src/main/scala/ee/hrzn/chryse/ExampleApp.scala b/src/main/scala/ee/hrzn/chryse/ExampleApp.scala
@@ -8,7 +8,7 @@ import ee.hrzn.chryse.platform.ecp5.LFE5U_85F
 import ee.hrzn.chryse.platform.ecp5.ULX3SPlatform
 import ee.hrzn.chryse.platform.ice40.IceBreakerPlatform
 
-object ExampleApp extends ChryseApp {
+private[chryse] object ExampleApp extends ChryseApp {
   class Top(implicit @annotation.unused platform: Platform) extends Module {}
 
   override val name                                  = "example"

diff --git a/src/main/scala/ee/hrzn/chryse/platform/ChryseTop.scala b/src/main/scala/ee/hrzn/chryse/platform/ChryseTop.scala
@@ -11,7 +11,7 @@ import ee.hrzn.chryse.platform.resource.ResourceData
 import scala.collection.mutable
 import scala.language.existentials
 
-trait ChryseTop extends RawModule {
+private[chryse] trait ChryseTop extends RawModule {
   override def desiredName = "chrysetop"
 
   case class ConnectedResource(

diff --git a/src/main/scala/ee/hrzn/chryse/platform/cxxrtl/BlackBoxGenerator.scala b/src/main/scala/ee/hrzn/chryse/platform/cxxrtl/BlackBoxGenerator.scala
@@ -7,7 +7,7 @@ import ee.hrzn.chryse.chisel.specifiedDirectionOf
 
 import java.io.Writer
 
-class BlackBoxGenerator(private val wr: Writer) {
+private[chryse] class BlackBoxGenerator(private val wr: Writer) {
   // Can we just add attributes somehow and output Verilog instead?
   //
   // -- I looked into this and there's many levels of things missing:

diff --git a/src/main/scala/ee/hrzn/chryse/platform/ecp5/LPF.scala b/src/main/scala/ee/hrzn/chryse/platform/ecp5/LPF.scala
@@ -5,7 +5,7 @@ import chisel3.experimental.Param
 import chisel3.experimental.StringParam
 import ee.hrzn.chryse.platform.resource.PinString
 
-final case class LPF(
+final private[chryse] case class LPF(
     ios: Map[String, (PinString, Map[String, Param])],
     freqs: Map[String, BigInt],
 ) {

diff --git a/src/main/scala/ee/hrzn/chryse/platform/ice40/PCF.scala b/src/main/scala/ee/hrzn/chryse/platform/ice40/PCF.scala
@@ -2,7 +2,7 @@ package ee.hrzn.chryse.platform.ice40
 
 import ee.hrzn.chryse.platform.resource.PinInt
 
-final case class PCF(
+final private[chryse] case class PCF(
     ios: Map[String, PinInt],
     freqs: Map[String, BigInt],
 ) {

diff --git a/src/main/scala/ee/hrzn/chryse/platform/resource/SPI.scala b/src/main/scala/ee/hrzn/chryse/platform/resource/SPI.scala
@@ -6,7 +6,7 @@ import chisel3.experimental.Param
 class SPI extends ResourceBase {
   // TODO: DSPI, QSPI
 
-  val cs    = ResourceData(Output(Bool()), invert = true)
+  val cs    = ResourceData(Output(Bool()), invert = true) // permitted to be unset
   val clock = ResourceData(Output(Clock()))
   val copi  = ResourceData(Output(Bool()))
   val cipo  = ResourceData(Input(Bool()))
@@ -42,14 +42,15 @@ class SPI extends ResourceBase {
   }
 
   def onPins(
-      csN: Pin,
+      csN: Pin = null,
       clock: Pin,
       copi: Pin,
       cipo: Pin,
       wpN: Pin = null,
       holdN: Pin = null,
   ): this.type = {
-    this.cs.onPin(csN)
+    if (csN != null)
+      this.cs.onPin(csN)
     this.clock.onPin(clock)
     this.copi.onPin(copi)
     this.cipo.onPin(cipo)
@@ -61,7 +62,7 @@ class SPI extends ResourceBase {
   }
 
   def data: Seq[ResourceData[_ <: Data]] =
-    Seq(cs, clock, copi, cipo) ++ Seq(wp, hold).filter(_.pinId.isDefined)
+    Seq(clock, copi, cipo) ++ Seq(cs, wp, hold).filter(_.pinId.isDefined)
 }
 
 object SPI {

diff --git a/src/main/scala/ee/hrzn/chryse/tasks/BuildTask.scala b/src/main/scala/ee/hrzn/chryse/tasks/BuildTask.scala
@@ -8,7 +8,7 @@ import ee.hrzn.chryse.platform.PlatformBoardResources
 import java.nio.file.Files
 import java.nio.file.Paths
 
-object BuildTask extends BaseTask {
+private[chryse] object BuildTask extends BaseTask {
   case class Options(
       program: Boolean,
       programMode: String,

diff --git a/src/main/scala/ee/hrzn/chryse/tasks/CxxsimTask.scala b/src/main/scala/ee/hrzn/chryse/tasks/CxxsimTask.scala
@@ -13,7 +13,7 @@ import java.nio.file.Paths
 import scala.collection.mutable
 import scala.sys.process._
 
-object CxxsimTask extends BaseTask {
+private[chryse] object CxxsimTask extends BaseTask {
   private val cxxsimDir = "cxxsim"
   private val baseCxxOpts = Seq("-std=c++17", "-g", "-pedantic", "-Wall",
     "-Wextra", "-Wno-zero-length-array", "-Wno-unused-parameter")

diff --git a/src/main/scala/ee/hrzn/chryse/verilog/InterfaceExtractor.scala b/src/main/scala/ee/hrzn/chryse/verilog/InterfaceExtractor.scala
@@ -3,7 +3,7 @@ package ee.hrzn.chryse.verilog
 import scala.collection.mutable
 import scala.util.matching.Regex
 
-object InterfaceExtractor {
+private[chryse] object InterfaceExtractor {
   private val reWhole: Regex =
     (raw"(?m)^module (\w+)\(" +
       raw"((?:\s*,?(?:\s*(?:input|output|inout)\s)?" +