Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

A 32-bit Kogge-Stone Adder is implemented in this design.

These are VHDL codes for a signed 4bit multiplier using 4bit adders. Base on Baugh-Wooley Method.

This is a VHDL code for 4bit multiplier using 4bit full adder circuit structurally modelled.

Digital Logic Design using pen and paper to design with Analog discovery 2, and using Verilog for synthesizing. these are some of my junior year labs for Digital Electronics

LTSpice simulation software is used to study the behavior of a Memristor. Different logic gates like NOR, NAND and XOR were modelled and simulated followed by the simulation of a memristor based full-adder.

This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert

4-bit Serial Adder/Subtractor with Parallel Load

Digital Design using Verilog

A project that simulate the circuits FullAdder and FullSubtractor

one cycle unsigned multiplier, don't cares of resources fpga or asic structures

4 bit ALU in verilog

➕➕ Arithmetic operations in most machines are performed in the ALU whereby logic gates and flipflops are combined so that they can subtract, multiply, and divide binary numbers. This circuit only implements the addition part, on four bit digits

A DIY 8 Bit Adder from single transistors

This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic

VHDL homework from FH Technikum Wien Master Embedded Systems course VHDL

The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.